1) Field of the Invention
This invention relates generally to fabrication of gate electrodes for semiconductor devices and more particularly to the fabrication of a T-shaped gate electrode for an MOS semiconductor device.
2) Description of the Prior Art
As devices are made smaller, a major problem with semiconductor manufacturing is the forming of smaller gate length or widths while maintaining gate performance and forming proper low resistance silicide contacts. The gate must be narrow at the substrate to reduce the channel length but must be wide enough so that proper salicide contacts can be formed to the top of the gate. This is particularly important as gate width (or lenghts decrease below 0.25 .mu.m). In order to increase the operation frequency of a device, it is in general required to shorten a length of a gate. However, further shortening of the gate length which is about 1 .mu.m causes gate resistance to increase due to a smaller aspect ratio. Therefore, in order to prevent increase of the gate resistance while shortening the gate length further, a method in which a section of the gate is formed to have a T form is mostly used.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,543,253(Park et al.) shows a T-gate process using one mask. PA1 U.S. Pat. No. 5,688,704(Liu) shows a T-gate using 2 dielectric layers. PA1 U.S. Pat. No. 5,861,327(Maeng et al.) teaches a T-gate using electroplating. PA1 U.S. Pat. No. 5,658,826(Chung), U.S. Pat. No. 5,496,779(Lee et al.) and U.S. Pat. No. 5,498,560(Sharma et al.) show T-gates using other processes.
However, an improved process is need for a T-gate electrode.